The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An instruction scheduling circuit of a processor may perform Out-of-Order issue of computer programming instructions (hereinafter, instructions). That is, the instruction scheduling circuit may issue the instructions in an order different from an original order of the instructions in a program. Out-of-order issue may be used to minimize the effects of result latency (such as load latencies) in a pipelined processor, and may be used to exploit instruction-level parallelism in a superscalar processor.
The number of instructions that may be issued by a processor during a clock cycle may be limited by an issue width of the processor. For example, a processor may be limited to issuing only three instructions per clock cycle.
When the number of instructions that are available for issue is larger than the issue width of the processor, the instructions scheduler may select a subset of the instructions that are available for issue during the clock cycle as the instructions to be issued.
Because an instruction may not be able to execute until one or more other instructions have produced their respective results, the order in which the instruction scheduling circuit selects instructions may affect the performance of the processor. The performance of the processor may also be affected by the amount of time the instruction scheduling circuit needs to select instructions.